Sreeram Duvvuru

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Publication Statistics

Publication period start
1995
Publication period end
1995
Number of co-authors
2

Co-authors
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Productive Colleagues
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Publications

Arya, Siamak, Sachs, Howard, Duvvuru, Sreeram (1995): An architecture for high instruction level parallelism. In: HICSS 1995 , 1995, . pp. 153-162. http://csdl.computer.org/comp/proceedings/hicss/1995/6930/00/69300153abs.htm

Duvvuru, Sreeram, Arya, Siamak (1995): Evaluation of a branch target address cache. In: HICSS 1995 , 1995, . pp. 173-180. http://csdl.computer.org/comp/proceedings/hicss/1995/6930/00/69300173abs.htm